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19-4736; Rev 0; 7/09
Integrated Powerline Communication Analog Front-End Transceiver and Line Driver
General Description
The MAX2981 powerline communication analog frontend (AFE) and line-driver IC is a state-of-the-art CMOS device that delivers high performance at low cost. This highly integrated design combines an analog-to-digital converter (ADC), digital-to-analog converter (DAC), adaptive gain control (AGC), filters, and line driver on a single chip. The MAX2981 substantially reduces previously required system components and complies with the HomePlug(R) 1.0 standard. Combined with Maxim's integrated PHY/MAC digital baseband, the device delivers the most flexible and cost-effective solution. The advanced design of the MAX2981 allows operation without external control, enabling simplified connection to a variety of HomePlug 1.0 digital PHY ICs. The MAX2981 is specified over the -40C to +105C automotive temperature range and is offered in a 64-pin lead-free LQFP package. The device is qualified to the AEC-Q100 Rev F automotive standard. o HomePlug 1.0 Compliant o Fully Integrated AFE and Line Driver o Fully Compatible with the MAX2982/MAX2986 o Pin-to-Pin Compatible with the MAX2980 o Seamless Interface to Third-Party PHY ICs o Fully Integrated, 10-Bit, 50Msps ADC and DAC o 56dB Adaptive Gain Control o Line Impedance Drive Capability as Low as 10 o Line-Driver Bypass Mode o 220mA in Rx Mode and 150mA in Tx Mode at 3.3V o -40C to +105C Operating Temperature Range o AEC-Q100 Rev F (Automotive) Qualified o 64-Pin LQFP Package
Features
MAX2981
Ordering Information
PART MAX2981GCB/V+ TEMP RANGE -40C to +105C PIN-PACKAGE 64 LQFP
Applications
Local Area Networking (LAN) Broadband-over-Powerline (BPL) Remote Monitoring and Control Energy Management Industrial Automation
/V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant part.
Pin Configuration
FREEZE RESET DGND 50 AGND AGND AGND AGND DVDD 49 AVDD AVDD 55 AVDD 54 STBY ENTX SWR I.C. 59 I.C. 58
Building Automation IPTV Distribution
AGND AVDD PLIP PLIN AGND AVDD CEXT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64
63
62
61
60
57
56
53
52
51
+
48 47 46 45 44 43 42
DAD0 DGND DAD1 DAD2 DVDD3 DAD3 DAD4 DVDD3 DGND DAD5 DAD6 DVDD3 DAD7 DAD8 DGND DAD9
Typical Operating Circuit appears at end of data sheet.
REXT AGND AGND PLOP
MAX2981
41 40 39 38 37 36 35 34 33
HomePlug is a registered trademark of HomePlug Powerline Alliance, Inc.
AVDD AGND PLON AVDD AVDD
17 AGND
18 REGOUT
19 DVDD
20 DGND
21 SDIO
22 SCLK
23 SHRCV
24 ENREAD
25 CS
26 DVDD
27 DGND
28 AGND
29 AVDD
30 DVDD3
31 CLK
32 AGND
LQFP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .....................................................-0.3V to +3.9V DVDD3 to DGND ...................................................-0.3V to +3.9V DVDD to DGND .....................................................-0.3V to +2.8V AGND to DGND.....................................................-0.3V to +0.3V All Other Pins..............................................-0.3V to (VDD + 0.3V) Current into Any Pin........................................................100mA Short-Circuit Duration (VREGOUT to AGND) ........................10ms Continuous Power Dissipation (TA = +70C) 64-Pin LQFP (derate 25mW/C above +70C)...........2000mW Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-40C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD3 = +3.3V, DVDD = REGOUT, VAGND = VDGND = VSHRCV = 0V, TA = -40C to +105C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Analog Supply Voltage Digital Supply Voltage Digital Supply Voltage SYMBOL VAVDD VDVDD3 VDVDD (Note 2) Receive mode, transmitter disabled, no signal applied Quiescent Supply Current IAVDD Transmit mode, receiver disabled, no signal and no load applied No clock VREGOUT VOH VOL VIH VIL IIH IIL N INL DNL IM3 Two tones at 17MHz and 18MHz at input 1VP-P differential voltage (Note 3) VIH = VDVDD VIL = 0V (Note 3) -5 10 2.3 0.8 -51.5 ISOURCE = 5mA ISINK = 5mA 2.0 0.8 +5 2.4 0.4 2.4 CONDITIONS MIN 3.0 3.0 2.4 220 mA 150 6 mA V V V V V A TYP MAX 3.6 3.6 UNITS V V V
Standby Supply Current Regulator Output Output-Voltage High Output-Voltage Low LOGIC INPUT Input High Voltage Input Low Voltage Input Leakage Current
ANALOG-TO-DIGITAL CONVERTER (ADC) Resolution Integral Nonlinearity Differential Nonlinearity Two-Tone 3rd-Order Distortion Bits LSB LSB dBc
DIGITAL-TO-ANALOG CONVERTER (DAC) Resolution Integral Nonlinearity Differential Nonlinearity Two-Tone 3rd-Order Distortion N INL DNL IM3 Two tones at 17MHz and 18MHz at output 1VP-P differential voltage 10 0.5 0.4 -54 Bits LSB LSB dBc
2
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD3 = +3.3V, DVDD = REGOUT, VAGND = VDGND = VSHRCV = 0V, TA = -40C to +105C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER RECEIVER Common-Mode Voltage Input Impedance Two-Tone 3rd-Order Distortion Receiver Gain Range Lowpass Filter -3dB Corner Frequency Lowpass Filter Ripple Highpass Filter -3dB Corner Frequency TRANSMITTER Common-Mode Voltage Output Impedance ZOUT Between PLOP/PLON and 0V at 12.5MHz (Note 3) Predriver gain = -6dB at 12.5MHz, VP-P at 10 single-ended output load Output Voltage Swing Predriver gain = 3dB at 12.5MHz, VP-P at 10 single-ended output load Predriver Output Voltage Swing Two-Tone 3rd-Order Distortion Lowpass Filter -3dB Corner Frequency Lowpass Filter Ripple Minimum Line Impedance Drive Capability Predriver Line Impedance Capability TIMING CHARACTERISTICS CLK Frequency CLK Fall to ADC Data Output CLK Fall to DAC Data Latch Time tADCO tDACI 50 2 3 MHz ns ns IM3 Line driver in bypass mode, predriver gain = 3dB; at 50 single-ended output load Two tones at 17MHz and 18MHz (Note 3) (Note 3) Single-ended output Line driver is in bypass mode, single-ended output 4 1.4 -50 23 2.6 10 50 -35 VP-P dBc MHz dB 1.6 3 1.4 VP-P V ZIN IM3 Rx (Note 3) (Note 3) (Note 3) Between PLIP or PLIN and 0V at 12MHz (Note 3) Two tones at 17MHz and 18MHz at input 1VP-P differential voltage 1.6 875 -52 56 23 2.6 2.4 V dBc dB MHz dB MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX2981
Note 1: Min and max values are guaranteed by design and characterization at TA = -40C and production tested at TA = +25C and +105C. Typical values are tested functionally at TA = +25C. Note 2: Bypass internal 2.4V regulator with 0.1F capacitor to DGND. Note 3: Typical values are guaranteed by design at TA = +25C.
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981
Pin Description
PIN 1, 5, 9, 10, 13, 17, 28, 32, 52, 53, 56, 57 2, 6, 12, 15, 16, 29, 54, 55, 60 3 4 7 8 11 14 18 19, 26, 49 20, 27, 34, 40, 47, 50 21 22 23 NAME AGND Analog Ground Analog Power-Supply Voltage. AVDD supply range is 3.0V to 3.6V. Bypass AVDD with a 0.1F capacitor to AGND. AC Powerline Positive Input AC Powerline Negative Input External Capacitor Connection. Connect a 10nF capacitor from CEXT to AGND. External Resistor Connection. Connect a 25k resistor from REXT to AGND. AC Powerline Positive Output AC Powerline Negative Output Voltage Regulator Output. Connect REGOUT to DVDD for normal operation. Digital 2.4V Voltage Input. Connect DVDD to REGOUT for normal operation. Digital Ground Serial Data Input/Output Serial Clock Input Receiver Shutdown Control. Drive SHRCV high to power down the receiver. Drive low for normal operation. Read-Mode Enable Control. Drive ENREAD high to place the DAD[9:0] bidirectional buffers in read mode. Data is transferred from the digital PHY to the AFE DAC. ENREAD signal frames the transmission. Active-High Carrier-Select Input. Drive CS high to initiate the internal timer. Digital Power-Supply Voltage. DVDD3 supply range is 3.0V to 3.6V. Bypass DVDD3 to DGND with a 0.1F capacitor as close as possible to the pin. 50MHz System Clock Input DAC/ADC Input/Output MSB Data Bit. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 8. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. FUNCTION
AVDD PLIP PLIN CEXT REXT PLOP PLON REGOUT DVDD DGND SDIO SCLK SHRCV
24 25 30, 37, 41, 44 31 33 35
ENREAD CS DVDD3 CLK DAD9 DAD8
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver
Pin Description (continued)
PIN 36 38 39 42 43 45 46 48 51 58, 59 61 62 63 64 NAME DAD7 DAD6 DAD5 DAD4 DAD3 DAD2 DAD1 DAD0 FREEZE I.C. ENTX SWR RESET STBY FUNCTION DAC/ADC Input/Output Data Bit 7. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 6. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 5. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 4. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 3. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 2. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 1. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output LSB Data Bit. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. Active-High Freeze-Mode Enable. Drive FREEZE high to place the adaptive gain control (AGC) in freeze mode. Drive FREEZE low if the the signal is not available for the companion baseband chip. Internally Connected. Leave these pins unconnected. Active-High Transmit Enable. Drive ENTX high to enable the transmitter. Drive ENTX low to place the transmitter in three-state. Active-High Register Write Enable. Drive SWR high to place the registers in write mode. Active-Low Reset Input. Drive RESET low to place the MAX2981 in reset mode. Set CLK in freerunning mode during a reset. The minimum reset pulse width is 100ns. Active-High Standby Input. Drive STBY high to place the MAX2981 in standby mode. Drive low for normal operation.
MAX2981
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981
Functional Diagram
MAX2981
PLIP VGA PLIN MUX PLOP LD PLON BUF LPF DAC DAD[9:0] LPF HPF AGC ADC
Detailed Description
The MAX2981 powerline communication AFE and linedriver IC is a state-of-the-art CMOS device that delivers high performance at low cost. This highly integrated design combines an ADC, DAC, AGC, filters, and line driver on a single chip as shown in the Functional Diagram. The MAX2981 substantially reduces previously required system components and complies with the HomePlug 1.0 standard. Combined with Maxim's integrated PHY/MAC digital baseband, the device delivers the most flexible and cost-effective solution. The advanced design of the MAX2981 allows operation without external control, enabling simplified connection to a variety of HomePlug 1.0 digital PHY ICs.
integrates reference voltages and biasing for the input differential signal.
Transmit Channel
The transmit channel consists of a 10-bit DAC, a LPF, and an adjustable-gain transmitter buffer and line driver. The DAC receives the data stream from the digital PHY IC through the mux block. The 50MHz, 10-bit DAC provides the complementary function to the receive channel. The DAC converts the 10bit digital stream to an analog voltage at a 50MHz rate. The LPF removes spurs and harmonics adjacent to the desired passband to help reduce the out-of-band transmitted frequencies and energy from the DAC output. The transmit buffer and line-driver blocks allow the output level of the LPF to obtain a level necessary to connect directly to the powerline medium, without the use of external amplifiers and buffers. The output level is adjustable from 1.4VP-P to 4.0VP-P differential. The line driver can drive resistive loads as low as 10 singleended.
Receive Channel
The receiver analog front-end consists of a variablegain amplifier (VGA), a lowpass filter (LPF), a highpass filter (HPF), and an AGC circuit. An ADC block samples the AGC output. The ADC communicates to the digital PHY chip through a mux block. The VGA reduces the receive channel input-referred noise by providing some signal gain to the AFE input. The filter blocks remove unwanted noise, and provide the anti-aliasing required by the ADC for accurate sampling. The AGC scales the signal for conversion from analog to digital. The scaling maintains the optimum signal level at the ADC input and keeps the AGC amplifiers out of saturation. The 10-bit ADC samples the analog signal at 50Msps and converts it to a 10-bit digital stream. The block fully
Line Driver Bypass
Use register R6B[2:1] to bypass the line driver. With the line driver bypassed, the output can drive a 50 singleended external load.
Digital Interface
The digital interface is composed of control signals and a 10-bit bidirectional data bus for the DAC and ADC. The control signals include a reset line, a transmit request, an I/O direction request, and a receiver shutdown control.
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver
Control Signals
Transmit Enable (ENTX) The ENTX line enables the transmitter of the MAX2981 AFE circuit. With ENTX and ENREAD driven high, data sent to the DAC through DAD[9:0] is conditioned and delivered onto the power line. Read Enable (ENREAD) The ENREAD line sets the direction of the data bus DAD[9:0]. With ENREAD high, data is sent from the digital PHY to the DAC in the MAX2981 AFE. A low on ENREAD sends data from the ADC to the digital PHY. Receiver Power-Down (SHRCV) The SHRCV line provides receiver shutdown control. A logic-high on SHRCV powers down the receiver section of the MAX2981 whenever the device is transmitting. The MAX2981 also features a transmit power-saving mode, which reduces supply current from 350mA to 150mA. To enter the transmit power-saving mode, drive SHRCV high 0.1s prior to the end of transmission. Connect SHRCV to ENTX and ENREAD for normal operation. Digital-to-Analog and Analog-to-Digital Converter Input/Output (DAD[9:0]) DAD[9:0] is the 10-bit bidirectional bus connecting the digital PHY to the MAX2981 DAC and ADC. The bus direction is controlled by ENREAD, as described in the Read Enable (ENREAD) section. AGC Control Signal (CS) The CS signal controls the AGC circuit of the receive path in the MAX2981. A logic-low on CS sets the gain circuit on the input signal to continuously adapt for maximum sensitivity. A valid preamble detected by the digital PHY raises CS to high. While CS is high, the AGC continues to adapt for an additional 8s; then the AGC locks the currently adapted level on the incoming signal. The digital PHY holds CS high while receiving a transmission, and then lowers CS for continuous adaptation for maximum sensitivity of other incoming signals. AGC Freeze Mode (FREEZE) Use the FREEZE signal to instantly lock the AGC gain. Clock (CLK) The CLK signal provides all timing for the MAX2981. Apply a 50MHz clock to this input. See the timing diagram (Figure 1) for more information. Reset Input (RESET) The RESET signal provides reset control for the MAX2981. To perform a reset, set CLK in free-running
tCLK 50MHz CLK tADCO ADC DATA OUT tDACI DAC DATA INPUT
MAX2981
Figure 1. ADC and DAC Timing Diagram
mode and drive RESET low for a minimum of 100ns. Always perform a reset at power-up.
Standby Control (STBY) The MAX2981 features a low-power, shutdown mode that is activated by STBY. Drive STBY high to place the MAX2981 in standby mode. In standby, the MAX2981 consumes only 20mA with a clock and 5mA without a clock.
MAX2981 Control Registers
MAX2981 Serial Interface The 3-wire serial interface controls the MAX2981 operation mode. The SCLK is the serial clock line for register programming. The SDIO is the I/O serial data input and output for register writing or reading. The SWR signal controls the write/read mode of the serial interface.
If SWR is high, the serial interface is in write mode and a new value can be written into the MAX2981 registers. Following SWR low-to-high transitions, data is shifted synchronously (LSB first) to registers on the falling edge of the serial clock (SCLK) as illustrated in Figure 2. Note that one extra clock (WR_CLK) is required to write the content of holding the buffer to the appropriate register bank. If SWR is low, the serial interface is in read mode and the value of the current register can be read. The read operation to a specific register must be followed immediately after writing to the same register. Following SWR high-to-low transitions, data is shifted synchronously (LSB first) to registers on the falling edge of the serial clock (SCLK) as illustrated in Figure 3. The MAX2981 has a set of six read/write registers; bits A2, A1, A0 are the register address bits.
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981
SWR
SWR
SDAT
D0
D1
D2
D15
A0
A1
A2 WR_CLK
SDAT
D0
D1
D2
D12
D13
D14
D15
SCLK
SCLK
Figure 2. Writing Mode Register Timing Diagram
Figure 3. Reading Mode Register Timing Diagram
Table 1. Register Addresses
REGISTER R1 (R/W) R2 (R/W) R3 (R/W) R4 (R/W) R5 (R/W) R6 (R/W) A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1
MAX2981 AFE Register Maps
Table 2. Register R1 Map
REGISTER BIT NO. R1B0 R1B1 R1B2 R1B3 R1B4 R1B5 R1B6 R1B7 R1B8 R1B9 R1B10 R1B11 R1B12 R1B13 R1B14 R1B15 DEFAULT High High Low Low Low Low Low Low Low Low Low Low Low Low Low Low COMMENT Active high, powers down the receiver when in transmit mode. Active high, powers down the transmitter when in receive mode. Active high, powers down the DAC when in receive mode. Active high, powers down the entire device. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved.
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981
Table 3. Register R2 Map
REGISTER BIT NO. R2B0 R2B1 R2B2 R2B3 R2B4 R2B5 R2B6 R2B7 R2B8 R2B9 R2B10 R2B11 R2B12 R2B13 R2B14 R2B15 DEFAULT Low Low Low High Low Low Low Low Low Low Low Low Low Low Low Low Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Active high, bypass the receive LPF. COMMENT
Table 4. Register R3 Map
REGISTER BIT NO. R3B0 R3B1 R3B2 R3B3 R3B4 R3B5 R3B6 R3B7 R3B8 R3B9 R3B10 R3B11 R3B[15:12] DEFAULT Low Low Low Low Low Low Low Low Low Low Low High 0111 Active high, place process tune in continuous mode. Otherwise active only during reset. Reserved. Reserved. Reserved. These set the predriver gain as follows setting 000 to 111: 3dB, 2dB, 1dB, 0dB, -1dB, -2dB, -3dB, -6dB R3B2 is the LSB. COMMENT
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981
Table 5. Register R4 Map
REGISTER BIT NO. R4B0 R4B1 R4B2 R4B3 R4B4 R4B5 R4B[10:6] R4B11 R4B12 R4B13 R4B14 R4B15 DEFAULT Low High High High Low Low 01011 High High High High Low Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. COMMENT
Table 6. Register R5 Map
REGISTER BIT NO. R5B[6:0] R5B[12:7] R5B13 R5B14 R5B15 DEFAULT Low Low Low Low Low Reserved. Reserved. Reserved. Reserved. Reserved. COMMENT
Table 7. Register R6 Map
REGISTER BIT NO. R6B0 R6B[2:1] R6B3 R6B4 R6B[6:5] R6B7 R6B8 R6B9 R6B[11:10] R6B[13:12] R6B14 R6B15 DEFAULT Low 00 Low Low 00 Low Low Low 10 00 High High Disable receiver highpass filter. Reserved. Reserved. Reserved. 00 internal LD active; 01 internal LD bypassed external load up to 1k and predriver current consumption 21mA; 11 internal LD bypassed external load 50 and predriver current consumption 42mA. Reserved. Active high, allow bypass of transmit LPF. COMMENT
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver
Applications Information
Interfacing to Digital PHY Circuit
The MAX2981 interfaces to the MAX2982/MAX2986 digital baseband IC using a bidirectional bus to pass the digital data to and from the DAC and ADC. Handshake lines help accomplish the data transfer and operation of the MAX2981. The application circuit diagram of Figure 4 shows the connection of the MAX2981 to the MAX2982/MAX2986 digital baseband chip.
Layout Considerations
A properly designed PCB is an essential part of any high-speed circuit. Use controlled-impedance lines on all frequency inputs and outputs. Use low-inductance connections to ground on all ground pins and wherever the components are connected to ground. Place decoupling capacitors close to all VDD connections. For proper operation, connect the metal exposed paddle at the back of the IC to the PCB ground plane with multiple vias.
MAX2981
DAD[9:0]
MAX2981
ENREAD* ENTX*
MAX2982/MAX2986
PLIP SHRCV CS POWERLINE HOT POWERLINE INTERFACE NEUTRAL PLOP PLIN SCLK SWR SDI0 50MHz CLK RESET STBY *SIGNALS CAN BE CONNECTED TO ONE CONTROL LINE. HOST INTERFACES
PLON
CLOCK
Figure 4. Interfacing the MAX2981 to the MAX2982/MAX2986
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Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981
Typical Operating Circuit
VDD 3 162 RECEIVER 10nF 162 2 4 VDD 10 5k DRIVER 10nF 100nF 5k 560pF 3 HPF 4 2 1 3 220pF 270pF 1 *10nF CAPACITOR ON NEUTRAL IS OPTIONAL 22nF 10nF* N HPF 1 VDD SPARK GAP 22nF 10nF L
1:1
POWERLINE
MAX2981
=
4 560pF
6.8H
5.6H 2
220pF
270pF
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 64 LQFP PACKAGE CODE C64+1 DOCUMENT NO. 21-0083
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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